1. Technical Field
The present invention relates to a semiconductor device.
2. Related Art
In relation to semiconductor devices having a plurality of field effect transistors (FETs), higher pair accuracy or namely higher relativity accuracy is often required between those FETs. For example, in relation to an operational amplifier or a differential circuit in comparator, or a pair FETs constituting a mirror circuit, high pair accuracy is required for reducing an input off-set voltage for such operational amplifier or such comparator.
Typical conventional semiconductor devices provided with a plurality of FETs include semiconductor devices described in Japanese Patent Laid-Open No. S62-81054 (No. 1987-81054) and Japanese Patent Laid-Open No. H06-13574 (No. 1994-13574).
FIG. 16 is a plan view, showing a semiconductor device described in Japanese Patent Laid-Open No. S62-81054. A semiconductor device 100 includes four FETs 101, 102, 103 and 104. Each of these FETs has an annular gate electrode 111, and a source electrode 112 and a drain region 113 provided in the outside and the inside thereof, respectively. In the FET 101 and the FET 103, the source electrode, the gate electrode and the drain electrode are electrically coupled with each other. A coupling situation between the FET 102 and the FET 104 is similar to that between the FET 101 and the FET 103.
Therefore, in the semiconductor device 100, a combination of the FET 101 and the FET 103 substantially functions as one FET and a combination of the FET 102 and the FET 104 substantially functions as another FET. Then, the FET composed of the FETs 101 and 103 and the FET composed of the FETs 102 and 104 constitute an FET pair.
FIG. 17 is a plan view, showing a semiconductor device described in Japanese Patent Laid-Open No. H06-13574. In a semiconductor device 200, an FET 210a and an FET 210b constituting an FET pair are also provided. The FETs 210a and 210b share a source region 201. The FET 210a has a gate electrode 202a and a drain region 203a. Similarly, the FET 210b has a gate electrode 202b and a drain region 203b. 
In addition to above, another prior art document related to the present invention is Japanese Patent Laid-Open No. H02-210864 (1990), in addition to Japanese Patent Laid-Open No. S62-81054 and Japanese Patent Laid-Open No. H06-13574.
In the semiconductor device 100 of FIG. 16, the FETs 101, 102, 103 and 104 are disposed to be spaced apart from each other. In such configuration, the pair accuracies of the FET-pairs composed of such FETs are more easily affected by a variation of impurity concentration in the diffusion layer in the substrate surface, as compared with the configuration, in which these are disposed closely with each other.
Besides, in the semiconductor device 200 of FIG. 17, geometries of the respective gate electrodes 202a and 202b are equivalent to a partial rectangular (more specifically, three in four sides that constitutes a rectangle). Therefore, channel-length in corners of the gate electrode 202a and 202b (for example, a section surrounded with dotted line L1) is different from that of other sections. Since an electric current flowing through the source and the drain tends to flow through a pass of shorter channel-length as possible, a deviation is created in such electric current. This cause being susceptive with an influence of a variation of an impurity concentration in the diffusion layer in the substrate surface, leading to a decrease in the pair accuracy of the FET-pair.
As described above, in relation to the conventional semiconductor device provided with a plurality of FETs, there is room for improving the pair accuracy of the FET-pair.